1. Field of the Invention
The present invention relates to substrates having improved electrical interconnection structures and fabrication methods thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
According to the current 3D IC chip stacking technologies, a silicon interposer is generally disposed between a packaging substrate and at least a semiconductor chip having a high routing density for electrically connecting the packaging substrate to the semiconductor chip, thereby achieving the purpose of integration of the semiconductor chip having a high routing density.
FIGS. 1A to 1E are schematic cross-sectional views showing a method for fabricating a silicon interposer 1 according to the prior art.
Referring to FIG. 1A, a silicon substrate body 10 having opposite first and second surfaces 10a, 10b is provided. A plurality of conductive through holes 100 are formed to penetrate the first and second surfaces 10a, 10b of the silicon substrate body 10 and a plurality of conductive pads 101 are formed on the first surface 10a and the conductive through holes 100.
Then, a passivation layer 11 is formed on the first surface 10a of the silicon substrate  body 10 and each of the conductive pads 101 is partially exposed from the passivation layer 11.
Thereafter, a seed layer 13 is formed on the passivation layer 11 and the conductive pads 101 and an electroplated copper layer 12 is then formed on the seed layer 13. The seed layer 13 can be made of Ti/Cu.
Subsequently, a resist layer 14 is formed on the electroplated copper layer 12 and portions of the electroplated copper layer 12 corresponding in position to the conductive pads 101 are exposed from the resist layer 14.
Then, a metal portion 15 is formed on each of the exposed portions of the electroplated copper layer 12. The metal portion 15 consists of a copper layer 150 bonded to the exposed portion of the electroplated copper layer 12, a nickel layer 151 bonded to the copper layer 150 and a gold layer 152 formed on the nickel layer 151. The gold layer 152 is the outermost layer of the metal portion 15.
Referring to FIG. 1B, the resist layer 14 and the electroplated copper layer 12 under the resist layer 14 are removed.
Referring to FIG. 1C, by using the nickel layer 151 and the gold layer 152 as an etch stop layer, an etching process is performed to remove the seed layer 13 around a periphery of each of the metal portions 15. As such, the metal portions 15 are electrically connected to the corresponding conductive pads 101, respectively.
Referring to FIG. 1D, an RDL (redistribution layer) process is performed on the second surface 10b of the silicon substrate body 10. That is, the first surface 10a of the silicon substrate body 10 and the metal portions 15 are bonded to a carrier 16 through an adhesive layer 160 and then an RDL structure 17 is formed on the second surface 10b of the silicon substrate body 10 and electrically connected to the conductive through holes 100.
Referring to FIG. 1E, a stealth dicing process is performed for singulation and then the carrier 16 and the adhesive layer 160 are removed, thus obtaining a plurality of silicon interposers 1. In particular, laser scanning is performed inside the silicon substrate body 10 to form embedded cutting lines along which the silicon substrate body 10 can be separated to form a plurality of silicon interposers 1. Thereafter, hot air is provided to cause the adhesive layer 160 to thermally expand, thereby facilitating to take out the silicon interposers 1. As such, the singulation process is completed.
Subsequently, referring to FIG. 1F, such a silicon interposer 1 can be applied in a 3D stacking process to form a semiconductor package 1′. In particular, the RDL structure 17 of the silicon interposer 1 is electrically connected to a plurality of bonding pads 180 of a packaging substrate 18 through a plurality of conductive elements 170, and an underfill 181 is formed between the silicon interposer 1 and the packaging substrate 18 to encapsulate the conductive elements 170. The bonding pads 180 of the packaging substrate 18 have a large pitch therebetween. Further, a plurality of electrode pads 190 of a semiconductor chip 19 are electrically connected to the conductive pads 101 through a plurality of conductive elements 15a and an underfill 191 is formed between the silicon interposer 1 and the semiconductor chip 19 to encapsulate the conductive elements 15a. The electrode pads 190 of the semiconductor chip 19 have a small pitch therebetween.
Referring to FIG. 1G, to form the conductive elements 15a, conductive bumps 153 containing a solder material are first formed on the metal portions 15. Then, the electrode pads 190 are aligned and connected to the conductive bumps 153. Thereafter, the conductive bumps 153 are reflowed.
However, in the above-described method of the silicon interposer 1, when the seed layer 13 is etched, a portion of the copper layer 150 of the metal portion 15 is also easily etched. Consequently, an undercut structure 15′, as shown in FIG. 1C, is formed underneath the nickel layer 151 and the gold layer 152. As such, after the silicon interposer 1 is separated from the carrier 16, as shown in FIG. 1E, some adhesive residual 160′ may remain on the undercut structure 15′ even if the silicon interposer 1 is cleaned by such as water. Therefore, as shown in FIG. 1G, during formation of the conductive bump 153 containing the solder material, the adhesive residual 160′ easily flows to the interface between the conductive bump 153 and the gold layer 152, thereby resulting in a poor bonding between the conductive pad 101 and the conductive bump 153 and consequently reducing the electrical interconnection quality between the semiconductor chip 19 and the silicon interposer 1. Accordingly, the reliability of the semiconductor package 1′ is reduced.
Therefore, how to overcome the above-described drawbacks has become critical.